(1) Field of the Invention
This present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form an anti-punch through, pocket region, for an N channel, metal oxide semiconductor (NMOS), device.
(2) Description of Prior Art
As the dimensions of metal oxide semiconductor field effect transistor (MOSFET), devices decrease, short channel effects (SCE), become more prevalent. For example the spreading of a source/drainxe2x80x94substrate depletion region, located at one end of a narrow channel length region, can approach the adjacent, source/drainxe2x80x94substrate depletion region, located at the other end of the narrow channel length region, resulting in unwanted leakage or punch through. In addition a threshold voltage (Vt), roll-off phenomena, featuring decreased Vt values with decreasing channel length, for a specific set of parameters such as gate dielectric thickness, channel doping, etc., can deleteriously influence the parametrics of narrow channel length devices.
One solution for the SCE phenomena has been the use of a pocket, or halo region, formed with the same conductivity type as the semiconductor substrate, but formed at a higher dopant concentration than the semiconductor substrate, in an area under the source/drain region. The pocket region limits the extent of the source/drainxe2x80x94substrate depletion region, and thus decreases unwanted leakages and possible punch through phenomena. In addition the unwanted Vt roll-off phenomena, prevalent with narrow channel length devices, is reduced when the implanted pocket regions are implemented. Pocket implant regions are usually accomplished in specific portions of a P type, semiconductor via implantation of P type ions, such as boron or indium. However the diffusivity of these P type ions can result in unwanted broadened, pocket region profiles, negated some of the benefits supplied by the pocket regions, when used for narrow channel length devices. This invention will describe a method of forming an indium pocket region for a narrow channel length device, however featuring a process step needed to confine the pocket implant profile, thus reducing the risk of punch through leakage, and Vt roll-off, for narrow channel length devices. Prior art, such Burr et al, in U.S. Pat. No. 5,650,340, as well as Burr et al, in U.S. Pat. No. 6,110,783, show methods of forming implanted pocket regions, however these prior arts do not describe the combination of process sequences used in this present invention, needed to form an implanted pocket region, with a confined profile, needed for narrow channel length, MOSFET devices.
It is an object of this invention to fabricate a NMOS device, featuring a narrow channel length region.
It is another object of this invention to form an indium pocket implant region, under the source/drain region of the NMOS device, to reduce SCE such as punch through leakage, and Vt roll-off.
It is still another object of this invention to place implanted antimony ions, into the indium pocket implant region, to confine the indium pocket profile.
In accordance with the present invention a method of fabricating a narrow channel length region, NMOS device, featuring an indium pocket implant region located under a source/drain region, and comprised with implanted antimony placed in the indium pocket n to restrict the broadening of the indium pocket profile, is described. After formation of a gate structure, on an underlying gate insulator layer, a first ion implantation procedure is used to place indium ions, in regions of a P type, semiconductor substrate, not covered by the gate structure. A second ion implantation procedure is next performed placing antimony ions into the same region of the P type semiconductor substrate, followed by a third ion implantation procedure, used for implantation of a first group of arsenic ions. Formation of insulator spacers on the sides of the gate structure, is followed by a fourth ion implantation procedure, placing a second group of arsenic ions, at a greater dopant concentration than the first set of arsenic ions, in a region of the P type semiconductor substrate not covered by the gate structure or by the insulator spacers. A subsequent anneal procedure activates the implanted ions and results in a profile of a lightly doped source/drain (LDD), region, comprised with the first set of arsenic ions, confined in a pocket implant region, comprised of indium ions, and featuring antimony ions located in the pocket implant region. The multi-component profile is located in, and confined to, a region in the P type semiconductor substrate not covered by the gate structure, or consumed by a heavily doped source/drain region, which in turn is comprised with the second set of arsenic ions, located in a region of the P type semiconductor substrate, not covered by the gate structure, or by the insulator spaces located on the sides of the gate structure.